1. Field of Use
The present invention relates to input/output systems and, more particularly, to systems which include duplicate units for improved reliability.
2. Prior Art
It is well-known to provide duplicate arithmetic units whose outputs are connected to comparison circuits for checking whether the results are correct. Such arrangements have been utilized in the prior art primarily for the purpose of error detection. Accordingly, the two units operated as a single unit and the single unit was, therefore, regarded as having failed in the event of a mis-compare in results. Other prior art systems have employed triplicate computer systems which connect to majority logic circuits for detecting the presence of errors and for establishing the failed system upon the occurrence of an error. These systems, while exceedingly reliable, normally are quite costly and complex.
Accordingly, it is an object of the present invention to provide a processing system which has a high degree of reliability and has a minimum of complexity.
It is a more specific object of the present invention to provide an input/output processing system in which it is possible to detect which processor within a pair has failed.